1. Field of the Invention
The present invention relates to a system LSI which debugs a program.
2. Description of the Related Art
Many system LSIs for high-end systems are equipped with high-performance, advanced processors. More and more system LSIs are being equipped with dual processors for further enhanced speed.
There is also available a system LSI which implements complicated functions by including a large number of small-scale processors instead of a high-performance processor and causing the processors to work in concert with each other (see, e.g., Japanese Laid-Open Patent Publication (Kokai) No. 2002-230065). This system LSI causes each processor to control a function module or causes the processors to execute a program for them to operate a function module in concert with each other. As described above, a small-scale processor executes a program alone or executes part of a program while working in concert with selected processors, thereby implementing a scenario based on a broader concept.
FIG. 6 is a block diagram showing the configuration of a conventional system LSI including a high-performance processor and small-scale processors. A system LSI 600 in FIG. 6 is mainly composed of a first processor 401, a ROM 402, a RAM 403, second processors 405 to 409, image processing modules 410 to 413, and an I/F module 414.
The first processor 401 is a high-performance processor which controls the entire system LSI 600 in accordance with a program. The ROM 402 stores a program. The RAM 403 is used as a work area for the processors 401 and 405 to 409 or used to pass data between component modules. A bus 404 sends and receives data between the components of the system LSI 600.
The second processors 405 to 409 are each a small-scale processor which executes an arbitrary program in accordance with an instruction from the first processor 401. The image processing modules 410 to 413 are function modules. The interface (I/F) module 414 is a function module which passes an instruction or data to/from the outside.
In the system LSI 600 with this configuration, the second processor 405 mainly controls the image processing module 410. Similarly, the second processors 406 to 408 mainly control the image processing modules 411 to 413 corresponding thereto, respectively. The second processor 409 mainly controls the interface module 414.
The first processor 401 debugs programs which are respectively executed by the second processors 405 to 409. In the processing, the first processor 401 first sends a command to single-step or notification of a breakpoint to each of the second processors 405 to 409 and suspends the programs serving as objects for debugging, which are being executed by the second processors 405 to 409, when respective predetermined steps end. The first processor 401 then acquires the statuses of the modules 410 to 414, which are mainly controlled by the second processors 405 to 409, and finds and fixes bugs in the programs executed by the second processors 405 to 409 by using the statuses as a resource to be referred to in the debugging.
However, the system LSI 600 has the following problem when debugging, by the above-described method, the programs executed by the second processors 405 to 409. More specifically, even if execution of the programs by the second processors 405 to 409 is suspended, it is impossible to acquire the correct statuses of the modules 410 to 414 originally desired to be monitored when the operation of the modules 410 to 414 is not suspended and still continues.